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features ? usable for automotive 12v/24v and industrial applications maximum high-speed data tr ansmissions up to 1 mbaud fully compatible with iso 11898 controlled slew rate standby mode txd input compatible to 3.3v short-circuit protection overtemperature protection high voltage bus lines protection, ?40v to +40v high speed differential receiver stage with a wide common mode range, ?10v to +10v, for high elect romagnetic immunity (emi) fully controlled bus lines, canh and canl to minimize electromagnetic emissions (eme) high esd protection at canh, canl hbm 8 kv, mm 300v 1. description the ata6660 is a monolithic circuit based on the atmel?s smart power bcd60-iii technology. it is especially designed for high speed can-controller (can-c) differen- tial mode data transmission between can-co ntrollers and the physical differential bus lines. figure 1-1. block diagram 4 rxd 5 vref 7 canh 6 canl 8 rs 2 gnd 3 vcc 1 txd txd input stage constant slope/ standby overtemperature and short circuit protection driver reference voltage 0.5*vcc receiver high-speed can transceiver ata6660 4582d?bcd?06/06
2 4582d?bcd?06/06 ata6660 2. pin configuration figure 2-1. pinning so8 txd gnd vcc rxd rs canh canl vref 1 2 3 4 8 7 6 5 table 2-1. pin description pin symbol function 1 txd transmit data input 2 gnd ground 3 vcc supply voltage 4 rxd receive data output 5 vref reference voltage output 6 canl low level can voltage input/output 7 canh high level can voltage input/output 8 rs switch standby mode/normal mode
3 4582d?bcd?06/06 ata6660 3. functional description the ata6660 is a monolithic circuit based on atmel?s smart power bcd60-iii technology. it is especially designed for high-speed differential mode data transmission in harsh environments like automotive and industrial applications. baudrate can be adjusted up to 1 mbaud. the ata6660 is fully compatible to the iso11898, the developed standard for high speed can-c (controller area network) communication. 3.1 voltage protection and esd high voltage protection circuitry on both line pi ns, canh (pin 7) and canl (pin 6), allow bus line voltages in the range of ?40v to +40v. esd protection circuitry on line pins allow hbm = 8 kv, mm = 300v. the implemented high voltage protection on bus line output/input pins (7/6) makes the ata6660 suitable for 12v automotive applications as well as 24v automotive applications. 3.2 slope control a fixed slope is adjusted to prevent unsymmetrical transient s on bus lines causing emc prob- lems. controlled bus lines, both canh and canl signal, will reduce radio frequency interference to a minimum. in well designed bus configurations the filter design costs can be reduced dramatically. 3.3 overcurrent protection in the case of a line shorts, lik e canh to gnd, canl to vcc, integrated short current limitation allows a maximum current of i canh_sc or i canl_sc . if junction temperature rises above 165c an internal overtemperature protection circuitry shuts down both output stages, the receiver will stay activated. 3.4 standby mode the ata6660 can be switched to standby mode by forcing the voltage vrs > 0.87 vcc. in standby mode the supply current will reduce dramatically, supply current during standby mode is typical 600 a (i vcc_stby ). transmitting data function will not be supported, bu t the opportunity will remain to receive data. a high-speed comparator is listening for activities on the bus. a domi- nant bus signal will force the output rxd to a low level in typical t drxdl = 400 ns. if the rs pin is not connected, causing through a broken connection to the controller, the ata6660 will switch to standby mode automatically. 3.5 high-speed receiver in normal mode a fast receiver circuitry combined with a resistor network is able to detect differ- ential bus line voltages v rec_th > 0.9v as dominant bit, differential bus line voltages v rec_th <0.5v as recessive bit. the wide receiver common mode range, ?10v to +10v, combined with a symmetrical differential receiver stage offers high immunity against elec tromagnetic interference. a typical hysteresis of 70 mv is implemented. dominant differential bus voltages forces rxd output (pin 4) to low level, recessive differential bus voltages to high level.
4 4582d?bcd?06/06 ata6660 3.6 txd input the input stage pin 1 (txd) is compatible for 3.3v output levels from new controller families. pull-up resistance (25 k ? ) forces the ic to recessive mode, if txd-pin is not connected. txd low signal drives the transmitter into dominant state. 3.7 transmitter a integrated complex compensation technique allows stable data transmission up to 1 mbaud. low level on txd input forces bus line voltages canh to 3.5v, canl to 1.5v with a termination resistor of 60 ? . in the case of a line short circuit, like canh to gnd, canl to vcc, integrated short current limitation circuitry allows a maxi mum current of 150 ma. if junction temperature rises above typical 163c an internal overtemperature protection shuts down both output stages, the receive mode will stay activated. 3.8 split termination concept with a modified bus termination (see figure 8-3 on page 10 ) a reduction of emission and a higher immunity of the bus system can be achieved. the one 120 ? resistor at the bus line end nodes is split into two resistors of equal value, i.e., two resistors of 60 ? . the resistors for the stub nodes is recommended with two resistors of 1.3 k ? . (for example 8 stub nodes and 2 bus end nodes) notice: the bus load of all the termination resistors has to stay within the range of 50 ? to 65 ? . the common mode signal at the centre tap of the termination is connected to ground via a capacitor of e.g., c split = 10 nf to 100 nf. a separate ground lead to the ground pin of the mod- ule connector is recommended.
5 4582d?bcd?06/06 ata6660 4. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters symbol conditions min. max. unit supply voltage v cc ?0.3 +6 v dc voltage at pins 1, 4, 5 and 8 v txd , v ref , v rs , v rxd ?0.3 v cc +0.3 v dc voltage at pins 6 and 7 v canh , v canl 0v < v cc < 5.25v; no time limit ?40.0 +40.0 v transient voltage at pins 6 and 7 ?150 +100 v storage temperature t stg ?55 +150 c operating ambient temperature t amb ?40 +125 c esd classification all pins hbm esd s.5.1 mm jedec a115a 3000 200 v v esd classification pin 6, 7 versus pin 2 hbm 1.5 k ? , 100 pf mm 0 ? , 200 pf 8000 300 v v 5. thermal resistance parameters symbol value unit thermal resistance from junction to ambient r thja 160 k/w 6. truth table vcc txd rs canh canl bus state rxd 4.75v to 5.25v 0 < 0.3 v cc 3.5v 1.5v dominant 0 4.75v to 5.25v 1 (or floating) < 0.3 v cc 0.5 v cc 0.5 v cc recessive 1 4.75v to 5.25v x > 0.87 v cc 0.5 v cc 0.5 v cc recessive 1 7. rs (pin 8) functionality slope control mode voltage and current levels v rs > 0.87 v cc standby i rs < | 10 a | v rs < 0.3 v cc constant slope control i rs 500 a
6 4582d?bcd?06/06 ata6660 8. electrical characteristics v cc = 4.75v to 5.25v; t amb = ?40c to +125c; r bus = 60 ? ; unless otherwise specified. all voltages referenced to ground (pin 2); positive input current. no. parameters test conditions pi n symbol min. typ. max. unit type* 1 supply current 1.1 supply current dominant v txd = 0v v rs = 0v 3i vcc_dom 45 60 ma a 1.2 supply current recessive v txd = 5v v rs = 0v 3i vcc_rec 10 15 ma a 1.3 supply current stand-by v rs = 5v 3 i vcc_stby 600 980 a a 2 transmitter data input txd 2.1 high level input voltage v txd = 5v v rs = 0v 1v txdh 2v cc + 0.3 v a 2.2 low level input voltage v txd = 0v v rs = 0v 1v txdl ?0.3 +1 v a 2.3 high level input current v txd = v cc 1i ih ?1 0 a a 2.4 low level input voltage v txd = 0v 1 i il ?500 -50 a a 3 receiver data output rxd 3.1 high level output voltage i rxd = ?100 a 4 v rxdh 0.8 v cc v cc va 3.2 low level output voltage i rxd = 1 ma 4 v rxdl 00.2 v cc va 3.3 short current at rxd v txd = 5v v rxd = 0v 4i rxds1 ?3 -1 ma a 3.4 short current at rxd v txd = 0v v rxd = 5v 4i rxds2 26maa 4 reference output voltage vref 4.1 reference output voltage normal mode vrs = 0v; ?50 a < i5 < 50 a 5v ref_no 0.45 v cc 0.55 v cc va 4.2 reference output voltage standby mode vrs = 5 v; ?5 a < i5 < 5 a 5v ref_stby 0.4 v cc 0.6 v cc va 5 dc bus transmitter canh; canl 5.1 recessive bus voltage v txd = v cc ; no load 6, 7 v canh ; v canl 2.0 2.5 3.0 v a 5.2 i o(canh)(reces) i o(canl)(reces) ?40v < v canh; v canl < 40v; 0v < v cc < 5.25v 6, 7 i o_reces ?5 +5 ma a 5.3 canh output voltage dominant v txd = 0v 6, 7 v canh 2.8 3.5 4.5 v a 5.4 canl output voltage dominant v txd = 0v 6, 7 v canl 0.5 1.5 2.0 v a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
7 4582d?bcd?06/06 ata6660 5.5 differential bus output voltage (v canh ? v canl ) v txd = 0v; r l = 45 ? to 60 ? ; v cc = 4.9v 6, 7 vdiff dom 1.5 2 3.0 v a 5.6 v txd = v cc ; no load 6, 7 vdiff rec ?500 +50 mv a 5.7 short-circuit canh current v canh = ?10v txd = 0v 6, 7 i canh_sc ?35 ?100 ma a 5.8 short-circuit canl current v canl = 18v txd = 0v 6, 7 i canl_sc 50 - 150 ma a 6 dc bus receiver canh; canl 6.1 differential receiver threshold voltage normal mode ?10v < v canh < +10v ?10v < v canl < +10v 6, 7 v rec_th 0.5 0.7 0.9 v a 6.2 differential receiver threshold voltage stand-by mode v rs = v cc 6, 7 v rec_th_stby 0.5 0.7 0.9 v a 6.3 differential input hysteresis 6, 7 v diff(hys) 70 mv a 6.4 canh and canl common mode input resistance 6, 7 r i 51525k ? a 6.5 differential input resistance 6, 7 r diff 10 30 100 k ? a 6.6 matching between canh and canl common mode input resistance 6, 7 r i_m ?3 +3 % a 6.7 canh, canl input capacitance 6, 7 c i 20 pf d 6.8 differential input capacitance 6, 7 c diff 10 pf d 6.9 canh, canl input leakage input current v cc = 0v v canh = 3.5v v canl = 1.5v 6, 7 i li(canh); i li(canl) 250 a a 7 thermal shut-down 7.1 shut-down junction temperature for canh/canl t j(sd) 150 163 175 c b 7.2 switch on junction temperature for canh/canl t j(sd) 140 154 165 c b 7.3 temperature hysteresis t hys 10 k b 8. electrical characteristics (continued) v cc = 4.75v to 5.25v; t amb = ?40c to +125c; r bus = 60 ? ; unless otherwise specified. all voltages referenced to ground (pin 2); positive input current. no. parameters test conditions pi n symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
8 4582d?bcd?06/06 ata6660 8 timing characteristics normal mode, v rs 0.3 v cc (see figure 8-1 on page 9 ) 8.1 delay txd to bus active v rs = 0v t d(txd-bus_on) 120 180 ns a 8.2 delay txd to bus inactive v rs = 0v t d(txd-bus_off) 50 100 ns a 8.3 delay txd to rxd, recessive to dominant v rs = 0v 6, 7 t d_activ(txd-rxd) 200 420 ns a 8.4 delay txd to rxd, dominant to recessive v rs = 0v t d_inactiv(txd-rxd) 180 460 ns a 8.5 difference between delay txd to rxd dominant to delay recessive t diff = t d_activ(txd-rxd) ? t d_inactiv(txd-rxd) t diff ?280 80 ns a 9 timing characteristi cs stand-by mode v rs 0.87 v cc 9.1 bus dominant to rxd low in stand-by mode v rs = v cc 4t drxdl 300 450 ns a 9.2 wake up time after stand-by mode (time delay between stand-by to normal mode and to bus dominant) txd = 0v vrs from 0v to v cc 6, 7 t wake_up 2 s a 10 standby/normal mode selectable via rs (pin 8) 10.1 input voltage for normal mode v rs = v cc 8v rs 0.3 v cc va 10.2 input current for normal mode v rs = 0v 8 i rs ?700 a a 10.3 input voltage for stand-by mode 8v stby 0.87 v cc va 8. electrical characteristics (continued) v cc = 4.75v to 5.25v; t amb = ?40c to +125c; r bus = 60 ? ; unless otherwise specified. all voltages referenced to ground (pin 2); positive input current. no. parameters test conditions pi n symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
9 4582d?bcd?06/06 ata6660 figure 8-1. timing diagrams txd vdiff canh canl rxd high low dominant (bus activ) recessive (bus inactive) high low 0.7vcc 0.3vcc 0.9v 0.5v t d (txd_bus_on) t d_activ(txd_rxd) t d_inactiv (txd_rxd) t d (txd_bus_off) dominant canh dominant canl
10 4582d?bcd?06/06 ata6660 figure 8-2. test circuit for timing characteristics figure 8-3. bus application with sp lit termination concept 2 3 4 8 7 6 5 1 ata6660 rxd vcc gnd txd rs canh canl vref c l =100pf r l =62 c=15pf c=100nf c=47f + 5v 234 8765 1 ata6660 rxd vcc gnd txd rs canh canl vref c=15pf c=100nf c=47f + 5v 234 8765 1 ata6660 txd gnd vcc rxd rs canh canl vref c=15pf can controller r l =60 r l =60 c split =10nf r l =60 r l =60 c split =10nf bus line end node bus line end node r l =1,3k c split =10nf r l =1,3k bus line stub node c=47f c=100nf can controller + 5v
11 4582d?bcd?06/06 ata6660 10. package information 11. revision history 9. ordering information extended type number package remarks ata6660-tapy so8 taped and reeled, pb-free ATA6660-TAQY so8 taped and reeled, pb-free technical drawings according to din specifications package so8 dimensions in mm 5.00 4.85 0.4 1.27 3.81 1.4 0.25 0.10 5.2 4.8 3.7 3.8 6.15 5.85 0.2 85 14 please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 4582d-bcd-06/06 ? put datasheet in a new template ? pb-free logo on page 1 deleted ? table ?ordering information? on page 11 changed 4582c-bcd-09/05 ? put datasheet in a new template ? pb-free logo on page 1 added ? heading rows on table ?absolute maximum ratings? on page 5 added ? table ?ordering information? on page 11 changed
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